1. Field of the Invention
The present invention relates to an apparatus for driving output signals from a DLL circuit, and more particularly to an apparatus for driving output signals from a DLL circuit, which has at least two driving parts for receiving the output signals from the DLL circuit.
2. Description of the Prior Art
As generally known in the art, a delay locked loop (DLL) circuit controls output timing of data read out from a synchronous memory device (hereinafter, referred to as “memory device”) on the basis of a clock externally applied to the memory device.
FIG. 1 is a block diagram showing a structure of a typical DLL circuit 100 by way of example.
As shown in FIG. 1, the DLL circuit 100 includes clock buffers 11 and 12, a delay line 13, a divider 14, a dummy delay line 15, a replica model part 16, a phase comparator 17, and a delay control part 18.
In FIG. 1, the clock buffers 11 and 12 receive external clocks clk and clkb. Herein, an output signal rclk of the clock buffer 11 is synchronized with a rising edge of the external clock clk, and an output signal fclk of the clock buffer 11 is synchronized with a rising edge of the external clock clkb.
The delay line 13 delays the phases of the external clocks having passed through the clock buffer 11.
The divider 14 divides the frequency of the external clock having passed through the clock buffer 12 at the ratio of 1/n (generally, n is set to ‘4’ or ‘8’). Herein, the division is mainly performed in order to reduce power consumption.
The dummy delay line 15 has the same structure as the delay line 13. Herein, since the dummy delay line 15 delays a signal divided by the divider 14, power consumption is lowered.
The replica model part 16 refers to a delay part obtained by modeling duration from application of the external clocks to arrival at the delay line 13 and duration until the output signals IRCLKDLL and IFCLKDLL of the delay line 13 are outputted to the outside of the memory device.
The phase comparator 17 detects a phase difference between the output signal of the divider 14 and the output signal of the replica model part 16. If rising edges of signals applied to the phase comparator 17 are coincident with each other, the DLL circuit is locked. At this time, the DLL clocks IRCLKDLL and IFCLKDLL lead about the length of ‘tAC’ over the external clocks.
The delay control part 18 controls the phases of signals applied to both the delay line 13 and the dummy delay line 15 in response to the output signal of the phase comparator 17.
FIG. 2 is a view showing an operation of the conventional apparatus for driving output signals from the DLL circuit, which employs the DLL circuit. The circuit shown in FIG. 2 has been employed for DDR2 SDRAM, DDR3 SDRAM, etc. having the ODT circuit. For reference, a signal Rasidle denotes a signal externally applied to the memory device. The signal Rasidle has a low level in an active mode and a high level in a precharge mode. A signal ODTEN denotes a signal outputted from the EMRS. The signal ODTEN enables an operation of the ODT.
As shown in FIG. 2, the output signal of the DLL circuit is simultaneously applied to both an ODT circuit 230 and an output driver 240 through a driving part 210.
Accordingly, conventionally, even when only the ODT circuit 230 is operated, the output driver 240 is enabled, thereby causing unnecessary power consumption.